市場調査レポート - 4970

高密度実装(HDP)技術(MCM、MCP、SIP)の動向と市場分析

High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends

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出版日 ページ情報 英文
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高密度実装(HDP)技術(MCM、MCP、SIP)の動向と市場分析 High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends
出版日: 2015年03月01日 ページ情報: 英文
概要

通信や集積回路、コンピューターの工業分野の市場調査で世界的に高い評価を得ております The Information Network(本社:ペンシルバニア州)では、HDP(高密度実装)技術とその市場について調査・分析を行い、まとめた報告書 “High-Density Packaging (MCM, MCP, SIP): Market Analysis and Technology Trends”を発行いたしました。

当報告書では、高密度実装(HDP)技術の概要、技術的課題、動向、用途別市場分析、競争環境、主要企業リスト、各種市場に関する今後の予測などについて、概略下記の構成でまとめております。

第 1 章 イントロダクション

第 2 章 エグゼクティブサマリー

第 3 章 技術に関する課題と動向

  • HDP 技術の概要
    • IC のマルチ統合の必要性
    • IC のマルチ統合の課題
  • 統合に関する技術的障壁
  • HDP の経済的な利点
  • 技術課題
    • 基質
    • 導体
    • 誘電体
    • Vias
    • ダイ接着
    • 2 次レベルの相互接続
    • 熱管理
    • 検査・管理
    • 設計
  • 3 次元モジュール
  • 超伝導インターコネクト
  • KGD
  • SIP
  • マルチチップ・パッケージ

第 4 章 用途

  • HDP の用途に関する概要
  • 軍事・航空
  • コンピューター&周辺機器
  • 通信
  • コンシューマ
  • 工業

第 5 章 競争環境

  • HDP の競争環境の概要
  • ジョイントベンチャーと企業間提携
  • HDP メーカー(80 社)

第 6 章 市場予測

  • マルチチップモジュールの概要
  • 発展促進因子
  • 代替実装技術
  • 世界の半導体市場予測
  • 世界の実装市場予測
  • 世界のMCM市場予測
    • 基質タイプ別予測
    • 用途別市場予測
    • 最終用途別市場予測

第 7 章 3 次元実装

  • インターコネクトのユーザビリティと可触性
  • ノイズ
  • 消費電力
  • 3D エレクトロニクスにおける垂直インターコネクション
  • エリア間相互接続スタックド MCM
  • 3 次元実装技術の限界
    • 熱管理
    • コスト
    • 設計の複雑性
    • Time to Delivery
目次

High-density packaging offer a host of benefits including performance improvements such as shorter interconnect lengths between die, resulting in reduced time of flight, lower power supply inductance, lower capacitance loading, less cross talk and lower off-chip driver power. High-density packages result in a smaller overall package when compared to packaged components performing the same function, hence resulting I/O to the system board is significantly reduced. By sweeping several devices onto one package, board complexity is simplified, thereby by reducing total opportunities for error at the board assembly level.

High-density packages have been subcategorized to better define their content and function.

An MCM is described as a package combining multiple IC's into a single system-level unit. The resulting module is capable of handling an entire function. These MCM packages typically have custom pin out configurations as well.

MCP, or multi-chip packages (sometimes referred to as few chip packages), are typically low lead count combinations of simple IC's. For these packages system control still occurs at the board level. They are primarily produced in volume in standard pin out and package configurations such as DIPs SOJs, QFPs and BGAs.

System-in-Package (SIP) is much more than an IC package containing multiple die. SIP products are fully functional systems or sub-systems in an IC package format. SIP may contain one or more IC chips (wirebonded or flip chip) plus other components that are traditionally found on the system mother board.

The increasing complexity and integration of electronic systems require advanced packaging and multichip module (MCM) techniques.

Various types of multichip packages (MCPs) have been used for many years, but costs have always kept volumes relatively low. Now, however, the felicitous combination of SRAM and flash memory chips in a single package for cell-phone applications is finally creating a high-growth, high-volume market for the multichip packaging.

Multichip packages hold high growth potential, but confusion with MCM technology makes exact forecasting difficult. Regardless of nomenclature, the forecasts offer proof that, by offering high performance in miniaturized spaces, MCPs make an attractive solution for next-generation wireless applications, primarily in mobile phones, but are also likely to become commonplace in various notebook computing applications.

SIP is basically an MCM, but it provides higher density and better time-to-market than the older MCM technology. While MCMs excel in reusability and flexibility, and SoCs excel at performance and density, the SIP is a compromise between the two. Testability and yield are the key deciding factors in the choice between SoC and SIP.

SIP technology is an ideal solution in markets that demand smaller size with increased functionality. However, SIP has the added benefit of compatibility with die design changes and integration of various die technologies (e.g., Si, GaAs, SiGe, SOI, MEMS and Optical) without the high cost and lead time associated with SoC development and manufacturing.

Table of Contents

Chapter 1 - Introduction

Chapter 2. Executive Summary

  • 2.1. Summary of Technology Issues
  • 2.2. Summary of Market Forecasts

Chapter 3 - Technology Issues and Trends

  • 3.1. Overview of HDP Technology
    • 3.1.1. Need for Multiple IC Integration
    • 3.1.2. Challenges of Multiple IC Integration
  • 3.2. Technical Constraints of Integration
  • 3.3. Economic Benefits of HDP
  • 3.4. Technology Issues
    • 3.4.1. Substrates
    • 3.4.2. Conductors
    • 3.4.3. Dielectrics
    • 3.4.4. Vias
    • 3.4.5. Die Attachment
    • 3.4.6. Next Level Interconnection
    • 3.4.7. Thermal Management
    • 3.4.8. Test and Inspection
    • 3.4.9. Design
  • 3.5. 3-D Modules
  • 3.6. Superconducting Interconnects
  • 3.7. Known Good Die
  • 3.8. System In Package (SIP)
  • 3.9. Multichip Package
  • 3.1. Package-On-Package (PoP)

Chapter 4 - Applications

  • 4.1. Semiconductor Industry by End Market
    • 4.1.1. Application Processors
    • 4.1.2. Microprocessors
    • 4.1.3. Programmable Logic Devices (PLDs)
    • 4.1.4. Analog Devices
    • 4.1.5. DRAM and NAND
  • 4.2. Semiconductor Industry by End Market
    • 4.2.1. Military and Aerospace
    • 4.2.2. Computer and Peripheral Equipment
    • 4.2.3. Communications
    • 4.2.4. Consumer
    • 4.2.5. Industrial

Chapter 5 - Competitive Environment

  • 5.1. Overview of the HDP Competitive Environment
  • 5.2. Joint Ventures and Cooperative Agreements
  • 5.3. HDP Manufacturers

Chapter 6 - 3-D-TSV Technology

  • 6.1. Driving Forces In 3D-TSV
  • 6.2. 3-D Package Varieties
  • 6.3. TSV Processes
  • 6.4. Critical Processing Technologies
    • 6.4.1. Plasma Etch Technology
    • 6.4.2. Cu Plating
    • 6.4.3. Thin Wafer Bondling
    • 6.4.4. Wafer Thinning/CMP
    • 6.4.5. Lithography
  • 6.5. Applications
  • 6.6. Limitations Of 3-DPackaging Technology
    • 6.6.1. Thermal Management
    • 6.6.2. Cost
    • 6.6.3. Design Complexity
    • 6.6.4. Time To Delivery
  • 6.7. Company Profiles

Chapter 7 - Market Forecast

  • 7.1. Overview of Multichip Modules
  • 7.2. Driving Forces
  • 7.3. System-in-Package (SiP)
  • 7.4. Flip Chip/Wafer Level Packaging
  • 7.5. Worldwide IC Market Forecast
  • 7.6. Worldwide Packaging Market Forecast
  • 7.7. Worldwide MCM Market Forecast
    • 7.7.1. Worldwide Forecast By Substrate Type
    • 7.7.2. Worldwide 3-D Through Silicon Via (TSV) Market
    • 7.7.3. Market Forecast By Application
    • 7.7.4. Market Forecast By End Use

List of Tables

  • 3.1: Multichip Modules Vs. Circuit Board Assemblies
  • 3.2: MCM Cost Comparison
  • 3.3: Substrate Technology Features
  • 3.4: Metal Conductors in MCMs
  • 3.5: Comparison of Thin-Film and Thick-Film Technologies
  • 3.6: Characteristics of Dielectric Materials
  • 3.7: CTE of Common Substrates and Adhesives
  • 3.8: Comparison of MCM Testers
  • 3.9: Density Comparisons of Single Package and 3-D MCM
  • 4.1: DRAM Supply Forecasts
  • 4.2: DRAM Demand Forecasts
  • 4.3: DRAM Demand Forecasts
  • 4.4: NAND Supply Forecasts
  • 4.5: NAND Demand Forecasts
  • 4.6: NAND Demand Forecasts
  • 4.7: PC Unit Shipment Forecast, 2011-2014
  • 5.1: MCM Manufacturers
  • 6.1: 3-D Mass Memory Volume Comparison Between Other Technologies and TI's 3D Technology In Cm3/Gbit
  • 6.2: 3-D Mass Memory Weight Comparison Between Other Technologies and TI's 3D Technology In Grams3/Gbit
  • 6.3: Institutions Working In The Area Of 3D TSV
  • 6.4: Companies Working In The Area OF 3D TSV
  • 7.1: WLP Demand By Device
  • 7.2: WLP Demand By Device
  • 7.3: Worldwide IC Package Market Forecast
  • 7.4: Worldwide MCM Market
  • 7.5: Worldwide MCM-C Market By Application
  • 7.6: Worldwide MCM-D Market By Application
  • 7.7: Worldwide MCM-L (MCM, SiP, MCP) Market By Application
  • 7.8: Worldwide MCM Market By Application

List of Figures

  • 1.1: Schematic Cross-Section View Of An MCM-D
  • 1.2: Cross-Section Of The RF And Microwave MCM-D Structure
  • 1.3: Thin Film Layers On The Planarized Core Layer Of MCM-SL/D Technology
  • 1.4: Flip Chip MCP
  • 1.5: SIP Cross Section
  • 3.1: IC Packaging Trends
  • 3.2: Technology Tree For HDP Types
  • 3.3: Form Factor Decrease By Package Type
  • 3.4: High Power Package Technology Roadmap
  • 3.5: Comparison Between Wire Bonding And Bump
  • 4.1: PoP 3chipstack Package
  • 4.2: Application Processor Revenue
  • 4.3: MPU Unit Shipments And Growth Trends
  • 4.4: ASIC and ASSP Design Starts
  • 4.5: PLD Share of Revenue by End Market
  • 4.6: Analog IC Revenue
  • 4.7: FCFBGA Memory Package
  • 4.8: FBGA 2-Chip Memory Package
  • 4.9: FBGA QDP Memory Package
  • 4.10: Semiconductor Unit Demand By End Market
  • 4.11: Military and Aerospace Semiconductor Revenue
  • 4.12: Computing (Data Processing) Semiconductor Revenue
  • 4.13: PC Price Decline Over The Past 10 Years
  • 4.14: Notebooks Declined For The First Time In 2012
  • 4.15: Tablets Surpassed 100 Million Units In 3 Years
  • 4.16: Comparison of desktop, notebook, and tablet shipments,
  • 4.17: Server shipments
  • 4.18: Wireless semi revenue
  • 4.19: Smartphone shipments
  • 4.20: Silicon Content Of Mobile Phones
  • 4.21: Consumer Semi Revenue
  • 4.22: Average Semi Content By Application
  • 4.23: Automotive Semiconductor Revenue
  • 4.24: Automotive Semiconductor Growth
  • 6.1: 3-D Through-Silicon Via (TSV)
  • 6.2: Silicon Efficiency Comparison Between 3D Packaging Technology And Other Conventional Packaging Technologies
  • 6.3: Comparison Between 2D And 3D Packaging In Terms Of The Accessability And Useablity Of Interconnection
  • 6.4: 3D Packages
  • 6.5: Through-Silicon Via (TSV)
  • 6.6: Moore's Law For Active Element Density
  • 7.1: Various System-In-Package (SiP) Applications
  • 7.2: SiP Structures
  • 7.1: Comparison Of SOC, MCM, SIP, And SOP
  • 7.2: Materials Integrated In The SOP Concept
  • 7.3: Wire Bond Versus Flip Chip
  • 7.4: Flip Chip And Wire Bond Equipment Forecast
  • 7.5: Growth In Copper Wire Bonding
  • 7.6: Projection of 3-D TSV Applications And Process Requirement
  • 7.7: Market Forecast of 3-D TSV Wafers
  • 7.8: Worldwide Market Of End Use Applications
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