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市場調査レポート - 4970

高密度実装(HDP)技術(MCM、MCP、SIP)の動向と市場分析

High-Density Packaging (MCM, MCP, SIP): Market Analysis and Technology Trends

発行 Information Network
出版日 ページ情報 英文
価格
高密度実装(HDP)技術(MCM、MCP、SIP)の動向と市場分析 High-Density Packaging (MCM, MCP, SIP): Market Analysis and Technology Trends
出版日: 2014年09月01日 ページ情報: 英文
概要

通信や集積回路、コンピューターの工業分野の市場調査で世界的に高い評価を得ております The Information Network(本社:ペンシルバニア州)では、HDP(高密度実装)技術とその市場について調査・分析を行い、まとめた報告書 “High-Density Packaging (MCM, MCP, SIP): Market Analysis and Technology Trends”を発行いたしました。

当報告書では、高密度実装(HDP)技術の概要、技術的課題、動向、用途別市場分析、競争環境、主要企業リスト、各種市場に関する今後の予測などについて、概略下記の構成でまとめております。

第 1 章 イントロダクション

第 2 章 エグゼクティブサマリー

第 3 章 技術に関する課題と動向

  • HDP 技術の概要
    • IC のマルチ統合の必要性
    • IC のマルチ統合の課題
  • 統合に関する技術的障壁
  • HDP の経済的な利点
  • 技術課題
    • 基質
    • 導体
    • 誘電体
    • Vias
    • ダイ接着
    • 2 次レベルの相互接続
    • 熱管理
    • 検査・管理
    • 設計
  • 3 次元モジュール
  • 超伝導インターコネクト
  • KGD
  • SIP
  • マルチチップ・パッケージ

第 4 章 用途

  • HDP の用途に関する概要
  • 軍事・航空
  • コンピューター&周辺機器
  • 通信
  • コンシューマ
  • 工業

第 5 章 競争環境

  • HDP の競争環境の概要
  • ジョイントベンチャーと企業間提携
  • HDP メーカー(80 社)

第 6 章 市場予測

  • マルチチップモジュールの概要
  • 発展促進因子
  • 代替実装技術
  • 世界の半導体市場予測
  • 世界の実装市場予測
  • 世界のMCM市場予測
    • 基質タイプ別予測
    • 用途別市場予測
    • 最終用途別市場予測

第 7 章 3 次元実装

  • インターコネクトのユーザビリティと可触性
  • ノイズ
  • 消費電力
  • 3D エレクトロニクスにおける垂直インターコネクション
  • エリア間相互接続スタックド MCM
  • 3 次元実装技術の限界
    • 熱管理
    • コスト
    • 設計の複雑性
    • Time to Delivery
目次

Abstract

High-density packaging offer a host of benefits including performance improvements such as shorter interconnect lengths between die, resulting in reduced time of flight, lower power supply inductance, lower capacitance loading, less cross talk and lower off-chip driver power. High-density packages result in a smaller overall package when compared to packaged components performing the same function, hence resulting I/O to the system board is significantly reduced. By sweeping several devices onto one package, board complexity is simplified, thereby by reducing total opportunities for error at the board assembly level.

High-density packages have been subcategorized to better define their content and function.

An MCM is described as a package combining multiple IC's into a single system-level unit. The resulting module is capable of handling an entire function. These MCM packages typically have custom pin out configurations as well.

MCP, or multi-chip packages (sometimes referred to as few chip packages), are typically low lead count combinations of simple IC's. For these packages system control still occurs at the board level. They are primarily produced in volume in standard pin out and package configurations such as DIPs SOJs, QFPs and BGAs.

System-in-Package (SIP) is much more than an IC package containing multiple die. SIP products are fully functional systems or sub-systems in an IC package format. SIP may contain one or more IC chips (wirebonded or flip chip) plus other components that are traditionally found on the system mother board.

The increasing complexity and integration of electronic systems require advanced packaging and multichip module (MCM) techniques.

Various types of multichip packages (MCPs) have been used for many years, but costs have always kept volumes relatively low. Now, however, the felicitous combination of SRAM and flash memory chips in a single package for cell-phone applications is finally creating a high-growth, high-volume market for the multichip packaging.

Multichip packages hold high growth potential, but confusion with MCM technology makes exact forecasting difficult. Regardless of nomenclature, the forecasts offer proof that, by offering high performance in miniaturized spaces, MCPs make an attractive solution for next-generation wireless applications, primarily in mobile phones, but are also likely to become commonplace in various notebook computing applications.

SIP is basically an MCM, but it provides higher density and better time-to-market than the older MCM technology. While MCMs excel in reusability and flexibility, and SoCs excel at performance and density, the SIP is a compromise between the two. Testability and yield are the key deciding factors in the choice between SoC and SIP.

SIP technology is an ideal solution in markets that demand smaller size with increased functionality. However, SIP has the added benefit of compatibility with die design changes and integration of various die technologies (e.g., Si, GaAs, SiGe, SOI, MEMS and Optical) without the high cost and lead time associated with SoC development and manufacturing.

Table of Contents

Chapter 1 Introduction

Chapter 2 Executive Summary

  • 2.1 Summary of Technology Issues
  • 2.2 Summary of Market Forecasts

Chapter 3 Technology Issues and Trends

  • 3.1 Overview of HDP Technology
    • 3.1.1 Need for Multiple IC Integration
    • 3.1.2 Challenges of Multiple IC Integration
  • 3.2 Technical Constraints of Integration
  • 3.3 Economic Benefits of HDP
  • 3.4 Technology Issues
    • 3.4.1 Substrates
    • 3.4.2 Conductors
    • 3.4.3 Dielectrics
    • 3.4.4 Vias
    • 3.4.5 Die Attachment
    • 3.4.6 Next Level Interconnection
    • 3.4.7 Thermal Management
    • 3.4.8 Test and Inspection
    • 3.4.9 Design
  • 3.5 3-D Modules
  • 3.6 Superconducting Interconnects
  • 3.7 Known Good Die
  • 3.8 System In Package (SIP)
  • 3.9 Multichip Package
  • 3.10 Package-On-Package (PoP)

Chapter 4 Applications

  • 4.1 Overview of HDP Applications
  • 4.2 Military and Aerospace
  • 4.3 Computer and Peripheral Equipment
  • 4.4 Communications
  • 4.5 Consumer
  • 4.6 Industrial

Chapter 5 Competitive Environment

  • 5.1 Overview of the HDP Competitive Environment
  • 5.2 Joint Ventures and Cooperative Agreements
  • 5.3 HDP Manufacturers
    • Advanced Packaging Systems
    • Aeroflex Laboratories
    • AMD
    • AMITEC
    • Amkor Electronics
    • Analog Devices
    • Appian Technology
    • AT&T
    • Ceramic Packaging
    • C-MAC MicroTechnology
    • CNM-IMB
    • Conexant
    • Control Data
    • CTM Electronics
    • CTS
    • David Sarnoff Research Center
    • Delco Electronics
    • Digital Equipment
    • Elpaq
    • Elpida
    • ERIM
    • Eureka
    • Fujitsu
    • GEC Plessey
    • General Electric
    • Hadco
    • Honeywell
    • Hughes
    • Hynx
    • Ibiden
    • IBM
    • ILC Data Device Corp.
    • IMEC
    • Infineon
    • Interconnect Systems
    • Interconnex
    • International Micro Industries
    • Integrated System Assemblies
    • Intersil
    • Kodak
    • Kyocera
    • Lexmark International
    • Lucent Technologies
    • MicroModule Systems
    • Micron
    • Mitsubishi
    • Motorola
    • nCHIP
    • NEC
    • Pacific Microelectronics
    • Pacific Microelectronics Centre
    • Packard-Hughes Interconnect
    • Panda Project
    • Phillips Laboratory
    • Philips
    • Pico Systems
    • Quadrant Technology
    • Renasas
    • RISH
    • Rockwell Avionics
    • Rogers
    • S3
    • Samsung Electronics
    • Sensonix
    • Sharp
    • Sheldahl
    • Shinko
    • S-MOS Systems
    • Spansion
    • Spectra
    • Tektronix
    • Teledyne Electronic Technologies
    • Tessera
    • Texas Instruments
    • Thomson Consumer Electronics
    • Toshiba
    • TRW
    • United Technologies
    • White Electronic Designs
    • W.L. Gore & Associates
    • Z Systems

Chapter 6 Market Forecast

  • 6.1 Overview of Multichip Modules
  • 6.2 Driving Forces
  • 6.3 Alternative Packaging Technologies
  • 6.4 Worldwide IC Market Forecast
  • 6.5 Worldwide Packaging Market Forecast
  • 6.6 Worldwide MCM Market Forecast
    • 6.6.1 Worldwide Forecast By Substrate Type
    • 6.6.2 Market Forecast By Application
    • 6.6.3 Market Forecast By End Use

Chapter 7 3-D Packaging

  • 7.1 Introduction
  • 7.2 Interconnect Usability and Accessibility
  • 7.3 Noise
  • 7.4 Power Consumption
  • 7.5 Vertical Interconnections in 3D Electronics
    • 7.5.1 Stacked Tape Carrier
    • 7.5.2 Solder Edge Conductors
    • 7.5.3 Thin Film Conductors on Face-of-a-Cube
    • 7.5.4 An Interconnection Substrate Soldered to the Cube Face
    • 7.5.5 Folded Flex Circuits
    • 7.5.6 Wire Bonded Stacked Chips
  • 7.6 Area Interconnection between Stacked MCMs
    • 7.6.1 Arrays of Contacts between Mcms With Through
      • Hole Vias
  • 7.7 Limitations of 3D Packaging Technology
    • 7.7.1 Thermal Management
    • 7.7.2 Cost
    • 7.7.3 Design complexity
    • 7.7.4 Time to Delivery

LIST OF TABLES

  • 3.1 Comparison of Three High-Density Packaging Approaches
  • 3.2 Multichip Modules Vs. Circuit Board Assemblies
  • 3.3 MCM Cost Comparison
  • 3.4 Substrate Technology Features
  • 3.5 Metal Conductors in MCMs
  • 3.6 Comparison of Thin-Film and Thick-Film Technologies
  • 3.7 Characteristics of Dielectric Materials
  • 3.8 Chip Interconnect Technology Features
  • 3.9 Chip Interconnection Techniques
  • 3.10 CTE of Common Substrates and Adhesives
  • 3.11 Comparison of MCM Testers
  • 3.12 Density Comparisons of Single Package and 3-D MCM
  • 5.1 MCM Manufacturers
  • 6.1 Worldwide IC Package Market Forecast
  • 6.2 Worldwide I/O Package Market Forecast
  • 6.3 Worldwide MCM Market
  • 6.4 Worldwide MCM-C Market By Application
  • 6.5 Worldwide MCM-D Market By Application
  • 6.6 Worldwide MCM-L (MCM, SiP, MCP) Market By Application
  • 6.7 Worldwide MCM Market By Application
  • 6.8 Worldwide Market Forecast Of End Use Applications
  • 7.1 Companies And Institutions Working In The Area Of 3D Packaging
  • 7.2 Companies And Institutions Working In The Area Of 3D Packaging
  • 7.3 3-D Mass Memory Volume Comparison Between Other Technologies And Texas 3D Technology In Cm3/Gbit
  • 7.4 3-D Mass Memory Weight Comparison Between Other Technologies And Texas 3D Technology In Grams3/Gbit

LIST OF FIGURES

  • 1.1 Schematic Cross-Section View Of An MCM-D
  • 1.2 Cross-Section Of The RF And Microwave MCM-D Structure
  • 1.3 Thin Film Layers On The Planarized Core Layer Of MCM-SL/D Technology
  • 1.4 Flip Chip MCP
  • 1.5 SIP Cross Section
  • 6.1 Comparison Of SOC, MCM, SIP, And SOP
  • 6.2 Materials Integrated In The SOP Concept
  • 6.3 Digital, RF And Optical Function Integration In One SOP Package
  • 6.4 Substrate Warpage Control
  • 6.5 Effect Of Elastic Modulus On Sop Package Substrate Warpage
  • 6.6 Area Assembly Pitch Reduction
  • 6.7 Summary Of Package/Board Materials With Modulus And CTE
  • 6.8 Low Loss Dielectrics And Future Requirements
  • 6.9 Eye Opening Measurements For Low Loss Dielectrics At 5 Gbps Data Rate
  • 7.1 Graphical Illustration Of The Silicon Efficiency Between MCMs And 3D Technology
  • 7.2 Silicon Efficiency Comparison Between 3D Packaging Technology And Other Conventional Packaging Technologies
  • 7.3 Comparison Between 2D And 3D Packaging Interms Of The Accessability And Useablity Of Interconnection
  • 7.4 Two Variants Of The Stacked Tape Carrier Vertical Interconnect (A) Stacked TAB On PCB. (B) Stacked TAB On Leadframe
  • 7.5 Three Variants Of The Solder Edge Conductors Vertical Interconnections. (A) Solder Edge Contacts. (B) Solder Filled Via.(C) Stacked PCB Leadframes.
  • 7.6 Thin Film Metal "T-Connects" For Vertical Interconnections
  • 7.7 Direct Laser Writing Process For Vertical Interconnections
  • 7.8 Texas Instruments Array TAB Leads Soldered To Bumps On A Silicon Substrate
  • 7.9 Schematic Diagram Of A PCB Solder To Tsops (Left) And (Right) A Cross Sectional View
  • 7.10 Schematic Diagram Showing How Ics Are Stacked And Interconnected Using A Flex Type Material
  • 7.11 Vertical Interconnection Approach Using Wire Bonding Techniques
  • 7.12 A Schematic Diagram Of Two Chips Stacked And Interconnected Using Wire Bonding (Upper) And (Lower) Top View Of The Upper Schematic Diagram
  • 7.13 A Schematic Diagram For An Array Of Contacts Between MCMs With Through-Hole Vias (Upper) And (Lower) Two MCMs Are Stacked By Applying A Mating Force
  • 7.14 Two Wafers Stacked Using Filled Vias Method
  • 7.15 Moore's Law For Active Element Density
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