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市場調査レポート
商品コード
1266873
高密度実装(MCM、MCP、SIP、3D-TSV):市場分析および技術動向High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends |
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高密度実装(MCM、MCP、SIP、3D-TSV):市場分析および技術動向 |
出版日: 2024年02月01日
発行: Information Network
ページ情報: 英文
納期: 2~3営業日
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当レポートでは、高密度実装について調査し、モバイルおよびIoT向けの先進パッケージング技術ソリューションを牽引する、より高い性能と密度に向けたパッケージング動向について解説しています。また、技術的な課題と動向、競合情勢、市場の予測などをまとめています。
The explosion of applications in the consumer and mobile space, internet of things (IoT) and the slowdown of Moore's law have been driving many new trends and innovations in packaging. The semiconductor industry now has to focus on system scaling and integration to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, system power consumption and system cost. This paradigm shift from chip-scaling to system-scaling will re-invent microelectronics, continue driving system bandwidth and performance, and help sustain Moore's Law. The challenge for semiconductor industry is to develop a disruptive packaging technology platform capable of achieving these goals.
This report discusses the packaging trends for higher performance and density driving advanced packaging technology solutions for mobile and IoT applications. One of the key enabling technologies to achieve these goals is thin 3D-packaging with integration. Developments have lately been made with various embedding technologies, such as eWLB/Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC's (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.