Flip chip packaging is currently growing at a 28% compound annual rate, and
the lithography and etch market will be major beneficiaries. Flip chip
packaging eliminates the need for wire bonding by placing the contact points
of the chip in direct contact with the packaging substrate and requiring the
stringent control of the placement of the chip on the substrate. This method
of advanced packaging of ICs offers advantages in size, signal speed, cost,
and reliability.
This report analyzes the manufacture of flip chips and analyzes the market to
2009. Lithography and wet etch equipment are also analyzed and forecast to 2009.
Table of Contents
Chapter 1 - Introduction
Chapter 2 - Executive Summary
Chapter 3 - Flip Chip/WLP Issues and Trends
3.1. Introduction
3.2. Wafer Bumping
3.2.1. Solder Bumps
3.2.1.1. Metallurgy
3.2.1.2. Deposition Of UBM
3.2.1.3. Sputter Etching
3.2.1.4. Photolithography
3.2.1.5. Solder Deposition
3.2.1.6. Resist Strip
3.2.1.7. UBM Wet Etch
3.2.1.8. Reflow
3.2.1.9. Flux Issues
3.2.2. Gold Bumps
3.2.2.1. Bump Processing
3.2.2.2. Bonding
3.2.2.3. Coplanarity
3.2.2.4. Conductivity
3.2.2.5. Thermal Properties
3.2.2.6. Size
3.2.2.7. Reliability
3.2.2.8. Cost Issues
3.2.3. Copper Pillar Bumps
3.2.4. Copper Stud Bumping
3.2.5. C4NP
3.3. Wafer Level Packaging
3.4. Pad Redistribution
3.5. Wafer Bumping Costs
3.5.1. Wafer Redistribution And Wafer Bumping Costs
3.5.2. WLCSP Hidden Costs
3.5.3. WLCSP Cost Per Good Die
3.5.4. Wafer-Level Underfill Costs
Chapter 4 - Lithography Issues And Trends
4.1. Issues
4.1.1. Technical Performance
4.1.2. Capital Investment
4.1.3. Cost Of Consumables
4.1.4. Throughput
4.1.5. Ease Of Use
4.1.6. Flexibility
4.1.7. Equipment Support
4.1.8. Resolution
4.1.9. Solder Bumping Capabilities
4.1.10. Gold Bumping Capabilities
4.2. Exposure Systems
4.2.1. Introduction
4.2.1.1. Reduction Steppers
4.2.1.2. Full-Field Projection
4.2.1.3. Mask Aligners
4.2.1.4. 1X Steppers
4.3. Competitive Technologies
4.3.1. Inkjet Printing
4.3.2. Stencil/Screen Printing
4.3.3. Electroless Metal Deposition
Chapter 5 - UBM Etch Issues And Trends
5.1. Introduction
5.2. Technology Issues And Trends
5.2.1. Process Flow
5.2.2. Etch Process
5.2.3. Etch Chemistry
5.3. Batch Versus Single-Wafer Etching
Chapter 6 - Metallization Issues and Trends
6.1. Introduction
6.2. Sputtering Metallization
6.2.1. Gold Bump
6.2.2. Solder Bumping
6.2.2.1. T i / Cu and TiW / Cu
6.2.2.2. Al / NiV / Cu
6.2.2.3. T i / N i (V) and TiW / Ni ( V )
6.2.2.4. Cr / Cr-Cu / Cu
Chapter 7 - Market Analysis
7.1. Market Drivers For Flip Chip And WLP
7.1.1. WLP For Small Die
7.1.2. WLP For Medium Die
7.1.3. WLP For Large Die
7.2. Market Opportunities
7.3. Challenges
7.4. Flip Chip Market
7.5. Lithography Market
7.5.1. Aligners Vs. Steppers
7.5.2. Market Analysis
7.6. Wet Etch Market
TABLES
3.1. Common UBM Stacks For Solder And Gold Bumping
3.2. Solder Bumping Guidelines
3.3. Gold Bumping Guidelines
3.4. Copper Bumping Guidelines
3.5. Comparison Of Solder Bumping Processes
4.1. Key Challenges For WLP Lithography
4.2. Lithography Tools By Vendor
5.1. UBM Film Etchants
5.2. Advantages Of Spin Processing
6.1. Common UBM Stacks For Gold And Solder Bumping
7.1. WLP Demand by Device (Units)
7.2. WLP Demand by Device (Wafers)
7.3. Comparison Of Mask Aligners Versus Steppers
7.4. Worldwide Lithography Forecast
7.5. Worldwide Forecast For UBM Etch Tools
7.6. Worldwide Forecast For UBM Etchants
FIGURES
3.1. C4 Chip Connections
3.2. 2005 Wafer Bump Technology Roadmap
3.3. Comparison Of Copper Pillar, Flip Chip, And WLP
