マルチビット/セルNANDフラッシュメモリーのリードアーキテクチャ

Read Architectures for Multi-bit per cell NAND Flash Memories

発行	Forward Insights
出版日	2009年09月	商品コード	98768
ページ情報	英文 36 Pages
価格	US$ 2,999 換算 ¥ 241,329 (税抜) PDF by E-mail (Unlimited User License)

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原文目次

Abstract

This report explores the theory, circuit elements, timings, and key design features of the conventional interleaved architecture versus the all bitline sensing architecture.

CONTENTS
LIST OF FIGURES
EXECUTIVE SUMMARY
INTRODUCTION
NAND FLASH READ ARCHITECTURES
- Conventional Read Architecture
  - Latch design
- All Bitline Sensing (ABL) Architecture
  - Sensing Design
- ABL Sensing vs. Conventional Read
  - Summary

REFERENCES
ABOUT THE AUTHOR
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List of Figures

Figure 1. NAND Architecture
Figure 3. Conventional Read: Essential Elements of the Page Buffer
Figure 4. Conventional Read Timing
Figure 5. Conventional Read Latches
Figure 6. Conventional Read: Latch characteristic for appropriate sizing
Figure 7. ABL sensing: Essential Elements of the Page Buffer
Figure 9. ABL sensing: the sense
Figure 10 Evaluation Time
Figure 11. Contributors to Parasitic Capacitance (Bitline cross-section)
Figure 12 Three adjacent bitlines and the effect of capacitive coupling between them
Figure 13 Yupin Effect
Figure 14. Cell working points
Figure 17 Programming Time for 2-bit/cell NAND Flash Memory
Figure 19 Energy Savings
Figure 20 3-bit/cell ABL Programming